On the Design of High Speed Parallel CRC Circuits using DSP Algorithams

Error correction codes provide a mean to detect and correct errors introduced by the transmission channel. Basically there are two categories of codes a).Block codes and b).convolution codes. Both the codes introduce redundancy by adding parity symbols to the message data. Cyclic redundancy check (CRC) codes are the subset of the cyclic codes. The hardware implementation of a CRC is a simple linear feedback shift register. LFSR circuit is simple and can runs at very high clock speeds, but it suffers from the limitation that the stream must be of bit-serial. CRC architectures for the generator polynomial are developed using DSP algorithms such as pipelining, unfolding and retiming. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. High-Speed parallel CRC increases the speed or throughput rate up to 25% when compared to the other techniques and reduce the hardware cost. Keywords— Cyclic redundancy check (CRC), linear feedback shift register (LFSR), pipelining, retiming, unfolding.